fpga4fun.com - JTAG 2 - How JTAG works
JTAG - 技术概览- XJTAG
JTAG Boundary Scan Basics White paper
![JTAG TAP/DAP State Machine [6]. | Download Scientific Diagram](https://www.researchgate.net/publication/261079643/figure/fig4/AS:667834657034252@1536235598361/JTAG-TAP-DAP-State-Machine-6.png "JTAG TAP/DAP State Machine [6]. | Download Scientific Diagram")
JTAG TAP/DAP State Machine [6]. | Download Scientific Diagram
VLSI
VLSI
Technical Guide to JTAG - XJTAG Tutorial
Securing the JTAG Interface | ASSET InterTech
Training JTAG Interface
Boundary-scan hardware controllers
The JTAG Test Access Port (TAP) State Machine - Technical Articles
JTAG(Joint Test Action Group) Wiki - FPGAkey
Boundary scan - Wikipedia
TAP and TAP Controller – VLSI Tutorials
The state machine of the JTAG TAP controller. | Download Scientific Diagram
TAP and TAP Controller – VLSI Tutorials
The many faces of the JTAG interface port – JTAG
a)JTAG TAP state machine, (b)Simplified ProASIC3 security | Download Scientific Diagram
File:JTAG TAP Controller State Diagram.svg - Wikimedia Commons
OpenOCD: OpenOCD JTAG Primer
2.1.2. JTAG Chip Architecture
